The subject matter disclosed herein relates to testing integrated circuits (ICs) during fabrication. More specifically, embodiments of the present disclosure relate to methods and test structures for testing at intermediate metal levels of an IC.
Each IC can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more chips of semiconductor substrate material. The quality and viability of a product including an IC can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of a first “metal level,” i.e., a metal wire for connecting several semiconductor devices together. BEOL generally includes fabrication processes following the formation of the first metal level, including the formation of all subsequent metal levels. To provide greater scaling and sophistication of the fabricated device, the number of metal levels can be varied to suit a particular application, e.g., by providing four to six metal levels, or as many as, in a further example, sixteen or more metal levels.
Products which include ICs therein must be tested before being provided to an end user. Conventionally, all metal levels of an IC chip must be fabricated before testing occurs, e.g., to provide enough electrical connections for the product to operate according to its specifications. Some design constraints or testing procedures can limit the number of detectable defects during a test after all metal levels in an IC chip have been fabricated. In some cases, one or more dedicated test structures can be embedded in an IC during manufacture to increase the number of testing variations and the amount of information yielded from a test. For example, a portion of each memory cell in the IC can be electrically coupled to a test switch to test each memory cell in alternating modes. Structurally incorporating multiple test switches into an IC chip can be disadvantageous because these structures greatly increase the amount of surface area occupied by test hardware. A fabricator may not be able to remove these structures or electrically couple them to other portions of the IC to provide different functions.